This invention relates to alignment marks and, more particularly, to the utilization of such marks in the fabrication of integrated circuits.
The fabrication of microminiature devices and circuits often requires that each of a set of masks (sometimes as many as 10 to 12) be successively aligned with high precision with respect to a semiconductor wafer. To obtain reasonable yields in the manufacture of very-high-resolution devices, sub-micron alignment tolerances are often required. Such tolerances are difficult to obtain by conventional manual means.
Automatic systems for achieving high-precision alignment of masks and wafers have been proposed. But designing these systems presents some formidable problems that arise, for example, from the fact that contrast and light levels from conventional alignment marks on typical wafers tend to be very low. Also, automatic systems as heretofore proposed may respond to small defects in the alignment patterns to give false indications. Hence these systems typically require the use of complex alignment patterns and extensive logic circuitry that in combination are designed to maximize the capability of the system to detect a true alignment-mark signal. Even when they function reliably, such systems tend in general to be relatively slow in operation.
Accordingly, the need arose in the process of fabricating integrated circuits for an alignment mark that would be characterized by high brightness, good contrast and relative freedom from degradation. It was recognized that such a mark if available would be an attractive basis for the design of an automatic alignment system.